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ISL9N304AP3/ISL9N304AS3ST
February 2002
PWM Optimized
ISL9N304AP3/ISL9N304AS3ST
N-Channel Logic Level UltraFET(R) Trench MOSFETs 30V, 75A, 4.5m
General Description
This device employs a new advanced trench MOSFET technology and features low gate charge while maintaining low on-resistance. Optimized for switching applications, this device improves the overall efficiency of DC/DC converters and allows operation to higher switching frequencies.
Features
* Fast switching * rDS(ON) = 0.0036 (Typ), VGS = 10V * rDS(ON) = 0.0060 (Typ), VGS = 4.5V * Qg (Typ) = 38nC, VGS = 5V * Qgd (Typ) = 13nC * CISS (Typ) = 4075pF
Applications
* DC/DC converters
DRAIN (FLANGE)
SOURCE DRAIN GATE D
GATE SOURCE DRAIN (FLANGE)
G S
TO-263
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 100oC, VGS = 4.5V)
TO-220
Ratings 30 20 75 74 20 Figure 4 145 0.97 -55 to 175 Units V V A A A A W W/oC
o
MOSFET Maximum Ratings TA = 25C unless otherwise noted
Continuous (TC = 25oC, VGS = 10V, RJA = 43oC/W) Pulsed PD TJ, TSTG Power dissipation Derate above 25oC Operating and Storage Temperature
C
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case TO-220, TO-263 Thermal Resistance Junction to Ambient TO-220, TO-263 Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 1.03 62 43
o
C/W C/W
oC/W o
Package Marking and Ordering Information
Device Marking N304AS N304AP Device ISL9N304AS3ST ISL9N304AP3 Package TO-263AB TO-220AB Reel Size 330mm Tube Tape Width 24mm N/A Quantity 800 units 50
(c)2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
ISL9N304AP3/ISL9N304AS3ST
Electrical Characteristics TA = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 25V VGS = 0V VGS = 20V TC = 150o 30 1 250 100 V A nA
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 75A, VGS = 10V ID = 74A, VGS = 4.5V 1 3 V 0.0036 0.0045 0.0060 0.0075
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(5) Qg(TH) Qgs Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge (VGS = 4.5V) VDD = 15V, ID = 20A VGS = 4.5V, RGS = 2.4 (VGS = 10V) VDD = 15V, ID = 20A VGS = 10V, RGS = 2.4 9 67 51 19 113 104 ns ns ns ns ns ns 14 77 33 20 137 79 ns ns ns ns ns ns VDS = 15V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 5V V = 15V DD VGS = 0V to 1V ID = 74A Ig = 1.0mA 4075 830 380 70 38 3.9 11 13 105 57 5.8 pF pF pF nC nC nC nC nC
Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
Unclamped Inductive Switching
tAV Avalanche Time ID = 3.8A, L = 3.0mH 255 s
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 74A ISD = 35A ISD = 74A, dISD/dt = 100A/s ISD = 74A, dISD/dt = 100A/s 1.25 1.0 27 16 V V ns nC
(c)2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
ISL9N304AP3/ISL9N304AS3ST
Typical Characteristic
1.2 POWER DISSIPATION MULTIPLIER 80
1.0 ID, DRAIN CURRENT (A) 60 VGS = 10V VGS = 4.5V 40
0.8
0.6
0.4
20
0.2
0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC)
0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Ambient Temperature
1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
ZJC, NORMALIZED THERMAL IMPEDANCE
PDM 0.1 t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 10-0 10-1
0.01 10-5
10-4
10-3
Figure 3. Normalized Maximum Transient Thermal Impedance
2000 TC = 25oC FOR TEMPERATURES 1000 IDM, PEAK CURRENT (A) ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: VGS = 10V I = I25 175 - TC 150
VGS = 5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
100
50 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
Figure 4. Peak Current Capability
(c)2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
ISL9N304AP3/ISL9N304AS3ST
Typical Characteristic (Continued)
150 PULSE DURATION = 80s 120 ID , DRAIN CURRENT (A) DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A) 120 150 VGS = 10V VGS = 4.5V VGS = 3.5V
90
90 VGS = 3V 60 TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0
60 TJ = 175oC 30 TJ = 25oC TJ = -55oC 0 1.5 2 2.5 3 3.5 4 VGS , GATE TO SOURCE VOLTAGE (V)
30
0
0.5
1
1.5
2
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
10 9 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 8 ID = 75A 7 6 ID = 20A 5 4 3 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
Figure 6. Saturation Characteristics
2 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.5
1
VGS = 10V, ID = 75A 0.5 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
Figure 7. Drain to Source On Resistance vs Gate Voltage and Drain Current
1.4 VGS = VDS, ID = 250A 1.2 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
Figure 8. Normalized Drain to Source On Resistance vs Junction Temperature
1.2 ID = 250A
1.0
1.1
0.8
0.6
1.0
0.4
0.2 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Gate Threshold Voltage vs Junction Temperature
Figure 10. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
(c)2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
ISL9N304AP3/ISL9N304AS3ST
Typical Characteristic (Continued)
6000 CISS = CGS + CGD C, CAPACITANCE (pF) VGS , GATE TO SOURCE VOLTAGE (V) 10 VDD = 15V 8
COSS CDS + CGD
6
1000
CRSS = CGD
4 WAVEFORMS IN DESCENDING ORDER: ID = 75A ID = 20A 0 15 30 45 60 75
2
VGS = 0V, f = 1MHz 300 0.1 1 10 30 VDS , DRAIN TO SOURCE VOLTAGE (V)
0 Qg, GATE CHARGE (nC)
Figure 11. Capacitance vs Drain to Source Voltage
250 VGS = 4.5V, VDD = 15V, ID = 20A 200 SWITCHING TIME (ns)
Figure 12. Gate Charge Waveforms for Constant Gate Currents
500 VGS = 10V, VDD = 15V, ID = 20A 400 SWITCHING TIME (ns)
tf tr 150 td(ON) 100 td(OFF) 50
td(OFF) 300
200 tf 100 td(ON) tr
0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE ()
0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE ()
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG -
BVDSS
VDS VDD
+
VDD
IAS 0.01
0 tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
(c)2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
ISL9N304AP3/ISL9N304AS3ST
Test Circuits and Waveforms (Continued)
VDS RL
VDD VDS
Qg(TOT)
VGS = 10V VGS Qg(5) VDD DUT Ig(REF) 0 VGS VGS = 1V Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
+
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
RGS
VGS
0
10%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
(c)2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
ISL9N304AP3/ISL9N304AS3ST
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T JM - T A ) P DM = -----------------------------Z JA
80 RJA = 26.51+ 19.84/(0.262+Area)
60 RJA (oC/W) 40 20 0.1 1 AREA, TOP COPPER AREA (in2) 10
(EQ. 1)
In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads.
Figure 21. Thermal Resistance vs Mounting Pad Area
R JA = 26.51 + ------------------------------------
19.84 ( 0.262 + A rea)
(EQ. 2)
(c)2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
ISL9N304AP3/ISL9N304AS3ST
PSPICE Electrical Model
.SUBCKT ISL9N304AP3 2 CA 12 8 3.3e-9 Cb 15 14 2.8e-9 Cin 6 8 3.68e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 32 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.61e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.98e-9 RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 19.8 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 0.5e-3 Rgate 9 20 2.31 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2.6e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),3))} .MODEL DbodyMOD D (IS=4e-11 N=1.04 RS=2.3e-3 TRS1=2e-3 TRS2=1e-6 + CJO=1.85e-9 M=0.51 TT=5e-11 XTI=1) .MODEL DbreakMOD D (RS=0.38 TRS1=2e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.45e-9 IS=1e-30 N=10 M=0.47) .MODEL MstroMOD NMOS (VTO=2.02 KP=200 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=1.55 KP=5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.31) .MODEL MweakMOD NMOS (VTO=1.31 KP=0.1 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23.1 RS=0.1) .MODEL RbreakMOD RES (TC1=1e-3 TC2=-7e-7) .MODEL RdrainMOD RES (TC1=1.7e-2 TC2=4.7e-5) .MODEL RSLCMOD RES (TC1=4.6e-3 TC2=5e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-2.9e-3 TC2=-8e-6) .MODEL RvtempMOD RES (TC1=-1.4e-3 TC2=1e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-6) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.1) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.1 VOFF=-0.4) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
GATE 1 RLGATE CIN
1 3 ;rev June 2001
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED 5 DRAIN 2
RSLC2
5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 -
(c)2002 Fairchild Semiconductor Corporation
+
DBODY
Rev. B, February 2002
Final Draft
ISL9N304AP3/ISL9N304AS3ST
SABER Electrical Model
REV June 2001 template ISL9N304AP3 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=4e-11,nl=1.04,rs=2.3e-3,trs1=2e-3,trs2=1e-6,cjo=1.85e-9,m=0.51,tt=5e-11,xti=1) dp..model dbreakmod = (rs=0.38,trs1=2e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.45e-9,isl=10e-30,nl=10,m=0.47) m..model mstrongmod = (type=_n,vto=2.02,kp=200,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=1.55,kp=5,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.31,kp=0.1,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6,voff=-3) DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-6) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.1) 10 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.1,voff=-0.4) RSLC1 c.ca n12 n8 = 3.3e-9 51 c.cb n15 n14 = 2.8e-9 RSLC2 c.cin n6 n8 = 3.68e-9 ISCL dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 32 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1
S1A S2A 13 8 S1B CA 13 + EGS 6 8 EDS 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 LGATE GATE 1 RLGATE CIN ESG + EVTEMP RGATE + 18 22 9 20 6 MSTRO 8 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY
LDRAIN DRAIN 2 RLDRAIN
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE RBREAK 18 RVTEMP 19
l.lgate n1 n9 = 5.61e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1.98e-9 res.rlgate n1 n9 = 56.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 19.8
12
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1e-3,tc2=-7e-7 res.rdrain n50 n16 = 0.5e-3, tc1=1.7e-2,tc2=4.7e-5 res.rgate n9 n20 = 2.31 res.rslc1 n5 n51 = 1e-6, tc1=4.6e-3,tc2=5e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.6e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-2.9e-3,tc2=-8e-6 res.rvtemp n18 n19 = 1, tc1=-1.4e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 3))
(c)2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
ISL9N304AP3/ISL9N304AS3ST
SPICE Thermal Model
REV June 2001 ISL9N304AP3 CTHERM1 TH 6 3e-4 CTHERM2 6 5 3.5e-3 CTHERM3 5 4 6.5e-3 CTHERM4 4 3 7.5e-3 CTHERM5 3 2 7.6e-3 CTHERM6 2 TL 3e-2 RTHERM1 TH 6 1e-4 RTHERM2 6 5 6e-3 RTHERM3 5 4 3e-2 RTHERM4 4 3 9.5e-2 RTHERM5 3 2 2.9e-1 RTHERM6 2 TL 4.5e-1
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model ISL9N304AP3 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =3e-4 ctherm.ctherm2 6 5 =3.5e-3 ctherm.ctherm3 5 4 =6.5e-3 ctherm.ctherm4 4 3 =7.5e-3 ctherm.ctherm5 3 2 =7.6e-3 ctherm.ctherm6 2 tl =3e-2 rtherm.rtherm1 th 6 =1e-4 rtherm.rtherm2 6 5 =6e-3 rtherm.rtherm3 5 4 =3e-2 rtherm.rtherm4 4 3 =9.5e-2 rtherm.rtherm5 3 2 =2.9e-1 rtherm.rtherm6 2 tl =4.5e-1 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
DISCLAIMER
FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM
OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R)
VCXTM
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
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This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4

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